1. Field of the Invention
The present invention relates to a fast data alignment queue structure for image block transfer, more particularly, to a specific structure of a display queue used in an image display window accelerator, whereby the structure provided by the present invention can simplify operating steps for "block transfer" of an image display card.
2. Description of Related Art
Nowadays, a window environment has become an essential software used in a computer system and so to accelerate the speed of image displaying has become an important issue. A usual manner to increase the speed of image displaying is to use a window accelerator. As a result, window commends can be directly transferred and provided by a built-in hardware in a display card without being transferred by a CPU (central processing unit), and therefore reducing a load for the CPU to thereby improve the display efficiency. The most important basic function of the window accelerator is without doubt BitBLT (bit block transfer). However, it is a very complicated and complex operation to align various transferred data after the block transfer has been processed. Accordingly, there exists a need for a method to simplify the data alignment.
Firstly, the principles and characteristics of block transfer will be explained as follows.
Referring to FIG. 1(a), if a block with a start address of (x1, y1) is to be transferred toward a lower-right direction to a such a position that the start address becomes (x2, y2), the block must be transferred by beginning with a point at the lower-right corner thereof. On the other hand, if a block with a start address of (x1', y1') is to be transferred toward an upper-left direction to such a position that the start address thereof becomes (x2', y2'), as shown in FIG. 1(b), then the block must be transferred by beginning with a point at the upper-left corner. An image block must be transferred by the manner described above to prevent the data thereof from being damaged.
Accordingly, the window accelerator must execute the operations of data reading, shifting, and writing sequentially as an example shown in FIG. 2. Since the capacitance of a DRAM of the window accelerator is typically 64 bits, this is the unit for data transfer operation. In FIG. 2, each cell indicates a byte, that is, 8 bits. The number in each cell is the address thereof. As shown in this figure, data are read by 64 bits and shifted toward right by two bytes (16 bits), and then the writing operation is sequentially executed by taking 64 bits as a unit. An FIFO buffer can be added therein to make it possible to read several sets of data in a memory cycle and then write them out at a time, so that a timing of the DRAM can accomplish a page mode operation. However, a conventional FIFO buffer, which comprises a plurality of levels, consists of a memory and a read-write controller, wherein a read or write operation can only be executed by a singlelevel at a time, and the executing direction can not be changed, that is, reverse reading or writing is not possible.
Eight possible shift conditions are shown in FIGS. 3(a) to (h), respectively. As shown in the figures, a set of 8 bytes of data stored with 8 addresses as address 0 to 7 may be transferred to address 0 to 7, 1 to 8, 2 to 9, 3 to 10, 4 to 11, 5 to 12, 6 to 13, or 7 to 14. A precise alignment of the data must be implemented through complex logic operation or transformation. The description above is only adaptable to a right-shift operation. It needs more complex data transfer to execute a left-shift operation since the read-write direction of the FIFO buffer is limited. Therefore, there exists a need for a simplified queue structure to reduce the complexity of the block transfer, and in the mean-while attain the effect for precise alignment.